High Thermal Die-Attach Paste Development For Analog Devices

2022-04-21 13:22:01 By : Ms. Renee Chan

A new die attach material can be applied to a large die size to improve the bulk and interface resistance.

Authors: Kiichiro Higaki, Toru Takahashi, Akinori Ono from Assembly Engineering Department Amkor Technology Japan, Inc. Keiichi Kusaka, Takayuki Nishi, Takeshi Mori from Information & Telecommunication Materials Research Laboratory, Sumitomo Bakelite Company, Limited Daisuke Koike, Masahiko Hori from Package Solution Technology Development Department, Electronic Devices & Storage Research Development Center, Toshiba Electronic Devices & Storage Corporation

Abstract: In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This limits the application window for adoption of these DA materials. Many semiconductor devices such as analog circuits, microcontroller units (MCUs) and application-specific integrated circuits (ASICs) that are widely used in electronic products do not require as much heat dissipation as high-power devices but could benefit from increased thermal capacity and can have larger die sizes. For such products, a DA material with a large amount of Ag powder is added to epoxy resins or acrylic resins to lower the elastic modulus. However, when a polymer is added to the system, the interface resistance increases between the DA material and the die, or between the DA material and the lead frame must be considered. As a result, even if the DA material includes a large amount of Ag, the thermal resistance of the entire package is not improved as expected due to the increase in resistance. To solve this problem, a new DA material concept has been jointly developed that can be applied to a large die size to improve the bulk and interface resistance. This paper will discuss material properties, improved thermal resistance of the package and reliability test results for this material.

Click here to read more.

Name* (Note: This name will be displayed publicly)

Email* (This will not be displayed publicly)

Smart software finds more EUV stochastic defects and missing vias, improving wafer yield.

It depends on whom you ask, but there are advantages to both.

Equipment companies and new battery chemistries among 132 startups that raised $3B.

Materials supply chain still bumpy and consumer buying has peaked for now, but growth continues.

The clock network is complex, critical to performance, but often it’s treated as an afterthought. Getting this wrong can ruin your chip.

Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.

Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.

Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.

Is there room for an even smaller version of a RISC-V processor that could replace 8-bit microcontrollers?

Why this is becoming a bigger issue, and what can be done to mitigate the effects.

Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.

How much do we pay for a system to be programmable? It depends upon who you ask.

From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.